| Course Type | Compulsory Course |
|---|
| Course Level | Bachelor's Degree |
|---|
| Year of Study | 2 |
|---|
| Semester | Third Term (Fall) |
|---|
| ECTS | 6 |
|---|
| Name of Lecturer(s) |
|
| Learning Outcomes |
At the end of this course, the students;
- Identify, formulate, and solve logic based engineering problems.
- Design logic based system.
- Convert lingustic control problem to logic problem, design and implement the hardware.
- Recognize logic component and design circuit these component.
|
| Mode of Delivery | Face to face |
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| Prerequisites | No |
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| Recommended Optional Programme Components | |
|---|
| Course Description | Digital Logic Design is the basic course on digital logic and digital design. following topics are covered in this course: Digital systems, numbers and number systems, codes, error detecting and correcting codes, Boolean algebra and Boolean functions, logic gates, gate level minimization, NAND/NOR realization, XOR, XNOR, combinational circuits, their analysis and design, adder-subtractor circuits, binary multipliers, decoders and encoders, synchronous sequential logic, flip-flops, analysis and design of clocked sequential circuits, state reduction, registers, shift registers, ripple counters, synchronous counters, memory elements, ROM, PLA, PAL and their usage, asynchronous sequential circuits. |
|---|
| Course Contents |
| WEEK |
TOPICS |
|
1st Week |
Digital systems, numbers and number systems, codes, error detecting codes. |
|
2nd Week |
Digital systems, numbers and number systems, codes, error detecting codes. |
|
3rd Week |
Error correcting codes, Boolean Algebra and Boolean Functions, logic gates |
|
4th Week |
Error correcting codes, Boolean Algebra and Boolean Functions, logic gates |
|
5th Week |
Gate level minimization, Karnaugh Maps, NAND/NOR realization, XOR, XNOR gates. |
|
6th Week |
Combinational circuits, their analysis and design, adder/subtractor circuits, binary multipliers, decoders, encoders. |
|
7th Week |
Combinational circuits, their analysis and design, adder/subtractor circuits, binary multipliers, decoders, encoders. |
|
8th Week |
Midterm Exam |
|
9th Week |
Synchronous sequential logic, flip-flops, analysis and design of clocked sequential circuits, state reduction. |
|
10th Week |
Synchronous sequential logic, flip-flops, analysis and design of clocked sequential circuits, state reduction. |
|
11th Week |
Registers, shift registers, ripple counters, synchronous counters. |
|
12th Week |
Registers, shift registers, ripple counters, synchronous counters. |
|
13th Week |
Memory and memory usage, ROM, PLA, their usage. |
|
14th Week |
Memory and memory usage, ROM, PLA, their usage. |
|
| Recommended or Required Reading | 1. Digital Design, M.Mano, 4th edition, Prentice-Hall.
2. Introduction to Logic Design, Marcovitz, McGraw-Hill, Second edition, 2005. |
|---|
| Planned Learning Activities and Teaching Methods |
- Questions/Answers
- Presentation
- Lecture
|
|---|
| Assessment Methods and Criteria |
|
Quantity |
Percentage (%) |
| Mid-term |
1 |
30 |
| Assignment |
1 |
6 |
| Quiz |
1 |
7 |
| Practice |
1 |
12 |
| Project |
1 |
13 |
| Attendance |
1 |
3 |
| Total(%) |
|
71 |
| Contribution of In-term Studies to Overall Grade(%) |
|
71 |
| Contribution of Final Examination to Overall Grade(%) |
|
29 |
| Total(%) |
|
100 |
|
| ECTS Allocated Based on Student Workload |
| Activities |
Quantity |
Duration (Hour) |
Total Workload (Hour) |
| Midterm exam |
1 |
2 |
2 |
| Preparation for Quiz |
2 |
4 |
8 |
| Individual or group work |
13 |
4 |
52 |
| Preparation for Final exam |
1 |
22 |
22 |
| Course hours |
14 |
4 |
56 |
| Preparation for Midterm exam |
1 |
18 |
18 |
| Laboratory (including preparation) |
2 |
2 |
4 |
| Final exam |
1 |
2 |
2 |
| Homework |
2 |
8 |
16 |
| Total Work Load | 180 |
| Total Work Load / 30 (h) | 6 |
| ECTS Credit of the Course | 6 |
|
| Language of Instruction | English |
|---|
| Work Placement(s) | No |
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