| Course Type | Elective Course |
|---|
| Course Level | Bachelor's Degree |
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| Year of Study | - |
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| Semester | - |
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| ECTS | 5 |
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| Name of Lecturer(s) |
- |
| Learning Outcomes |
At the end of this course, the students;
- Learns and understands the current situation of the Digital Circuit Design industry.
- Learns and understands FPGA based Digital Circuit design and application
- Ability to research the latest technology issues of FPGA based Digital Circuits; preparing and giving presentations; Gains the ability to read and write articles in FPGA-based circuits
- Gains experience and skills in using Software Tools in FPGA-based systems.
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| Mode of Delivery | |
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| Prerequisites | Yes(BENG219) |
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| Recommended Optional Programme Components | |
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| Course Description | This course comprises internal architecture of Field Programmable Gate Arrays (FPGAs), associated simulation and design software, VHDL language, principles of implementation of combinatorial circuits and Finite State Machines (FSMs) within FPGAs, FPGA based design and implementation of decoders, encoders, muxes, demuxes, comparators, parity circuits, adder-subtractors, timers and counters, shift registers, memory blocks and their derivers, AD and DA derivers, signal and control ports, FPGA based FSM applications using flip-flops and latches. |
|---|
| Course Contents |
| WEEK |
TOPICS |
|
1st Week |
Number systems (Binary, octal, hexadecimal, sign-magnitude notation, two's complement notation, addition and subtraction, BCD) |
|
2nd Week |
Review and review of logic gates, combinational circuits, Karnaugh maps, flip-flops, propagation delays, timing diagrams |
|
3rd Week |
Moore and Meely Finite State Machines (FSM), State Diagram based design |
|
4th Week |
Hardware Design Languages ??(HDL), Simulation tools, HDL-based design flow, VHDL, program structure, concurrency, types, constants, arrays, IPs, FPGA technology, FPGA architectures, principles of FPGA-based design |
|
5th Week |
Hardware Design Languages ??(HDL), Simulation tools, HDL-based design flow, VHDL, program structure, concurrency, types, constants, arrays, IPs, FPGA technology, FPGA architectures, principles of FPGA-based design |
|
6th Week |
Decoders, Encoders, muxes, demuxes and their FPGA based implementations. |
|
7th Week |
FPGA based circuit design such as Comparators, Parity circuits, Adders-subtractors |
|
8th Week |
Midterm Exam |
|
9th Week |
FPGA based clock and waveform generation, FPGA based up-down counter, step counters, Shift registers |
|
10th Week |
Design and implementation of Finite State Machines (FSMs) on FPGAs using flip-flops and Latch |
|
11th Week |
Design and implementation of Finite State Machines (FSMs) on FPGAs using flip-flops and Latch |
|
12th Week |
FPGA-based synchronous and asynchronous FSMs. |
|
13th Week |
FPGA-based multi-bit registers and latches, RAMs |
|
14th Week |
Connecting AD and DA converters to FPGAs and other signal connection ports. |
|
| Recommended or Required Reading | John F. Wakerly, Digital Design Principles and Practices,4th edition, 2016, Prentice Hall
M. Morris Mano,Michael Ciletti,Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog,2017, Pearson |
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| Planned Learning Activities and Teaching Methods |
- Lecture
- Problem Solving
- Experiment
- Report Preparation
|
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| Assessment Methods and Criteria |
|
Quantity |
Percentage (%) |
| Mid-term |
1 |
30 |
| Assignment |
10 |
30 |
| Total(%) |
|
60 |
| Contribution of In-term Studies to Overall Grade(%) |
|
60 |
| Contribution of Final Examination to Overall Grade(%) |
|
40 |
| Total(%) |
|
100 |
|
| ECTS Allocated Based on Student Workload |
| Activities |
Quantity |
Duration (Hour) |
Total Workload (Hour) |
| Midterm exam |
1 |
2 |
2 |
| Preparation for Quiz |
|
|
|
| Individual or group work |
14 |
3 |
42 |
| Preparation for Final exam |
1 |
20 |
20 |
| Course hours |
14 |
3 |
42 |
| Preparation for Midterm exam |
1 |
10 |
10 |
| Laboratory (including preparation) |
13 |
2 |
26 |
| Final exam |
1 |
2 |
2 |
| Homework |
3 |
3 |
9 |
| Total Work Load | 153 |
| Total Work Load / 30 (h) | 5.1 |
| ECTS Credit of the Course | 5 |
|
| Language of Instruction | - |
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| Work Placement(s) | No |
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